1. Field of the Invention
The present invention relates generally to digital-to-analog converters (DAC) and more particularly to reducing the glitch energy at DAC outputs.
2. Background
Glitch energy is one measure of the output signal quality of a DAC. Glitch energy represents the difference in the amount of energy delivered to the output during a step in output level as compared to an ideal output step. Non-ideal DAC output transitions can result in signal distortions such as the output initially moving in a direction opposite that of the desired step, overshooting the step, or ringing after the step. The effect of these non-ideal transitions depends on the application of the DAC. In DACs used for driving graphics and video display devices, excessive glitch energy can cause color shifts at the borders of objects causing sparkles on the display screen.
DACs of the type commonly used for driving video and graphics display devices are called current mode DACs. Current mode DACs are made up of many current sources (e.g., 255 in an 8-bit linearly weighted DAC), each current source representing one or more least significant bits (LSB) of the DAC output. The currents are steered to either the output or to another node, typically ground, depending on the digital input code presented to the DAC for conversion. As shown in FIG. 1, the currents are summed and then converted to an output voltage by a resistor (RLOAD) connected from the output pad to ground. The digital input code presented to the DAC typically controls the amount of current routed to the output in two ways. First, binarily weighted, and second linearly weighted. In a binary system, each bit of the digital input code controls an amount of current that corresponds to the significance of that bit in the digital input code. That is, bit 0 (the LSB) of the digital input code, switches 20, i.e., one unit of current, bit 1 switches 21, i.e., 2 units of current, and bit n switches 2n units of current. These units of current are often referred to as an LSB of current because the smallest unit of current is that controlled by the LSB of the digital input code. This type of system requires N switches for an N-bit code, which is the fewest possible in this type of design. However, it is difficult to make all the sources and switches sufficiently matched that good DAC linearity is maintained for code transitions between (2Mxe2x88x921) and (2M) for large M.
A least significant bit defines the smallest current source and switch size. As the amount of current is increased in the binary section of the DAC, the size of the transistors (or the number of elements in parallel) is increased proportionately.
In a linear system, data input codes, specifying non-zero currents, are decoded so as to enable one or more equal valued current sources. As the code increases, a new unit of current is added to the total (see Table 1 below). If the system is entirely linear, each unit of current is an LSB and therefore 2Nxe2x88x921 switches are required for an N-bit digital input code (no switch for digital input code 0). Because all switches are substantially identical, linearity is easier to achieve than in a fully binarily weighted DAC. Unfortunately, a fully linearly weighted DAC requires a large amount of chip area and is therefore relatively expensive to implement.
To convert a digital input code to the control signals needed to drive the large number of current switches required by a linearly weighted DAC, a translation, referred to as a thermometer code is used. A thermometer decoder refers to an information processing network that takes an N bit input and produces a 2N bit output as shown in Table 1 below.
Many DAC designs use a combination of both binary and linear switch control. The DAC digital input code is xe2x80x9csegmentedxe2x80x9d between binary and linear switch control. Binary is used for the least significant segment and linear for the most significant segment. Binary switch control is area efficient but tends to generate non-ideal output transitions because of the difficulty of balancing currents in differently sized switches. Linear switch control consumes more chip area but introduces fewer non-idealities into the output signal. The segmented DAC architecture provides a tradeoff between chip area and output signal quality. Examples of segmentation of an 8-bit DAC are given in Table 2 below.
The ideal transition of a DAC output when the input switches from code to code is a simple step with some reasonable rise time shorter than the smallest code duration. The actual transition may be significantly different. The difference from ideal in the energy transferred is the glitch energy.
The largest source of glitches is the timing skew between turning off one set of current switches while turning on a different set. This is usually due to the hazard in a binary encoding, for instance switching from code 00001111 to code 00010000. The code can briefly go to 00000000 or 00011111 causing overshoot or undershoot. Other causes of glitches are charge sharing in the switch (explained below) and capacitive feedthrough in the current switch from the switch driver. FIG. 2(a) shows an ideal step and FIG. 2(b) shows an example of a non-ideal transition.
FIG. 3 shows a block diagram of a conventional 8-bit DAC. This example uses 4xe2x80x944 segmentation, i.e., 4 bits that are binarily decoded and 4 bits that are linearly decoded. The lower 4 bits and the decoded upper 4 bits are clocked into flip-flops to synchronize the output transitions between the bits. The flip-flops are connected to the switch drivers that control the current switches. The outputs of the current switches are summed and sent to the output pad.
FIG. 4 shows a conventional current switch control circuit along with other DAC circuit elements. The data input comes from the lower bits or from a thermometer decoder for the most significant bits. The data is clocked into a D-type flip-flop (DFF) 402 to synchronize the data to the clock. DFF 402 drives the current switch control signal generator that controls a pair of current steering transistors, PFET 410 and PFET 412. PFET 414 is the current source whose current magnitude is set by the bias signal ISET and the size of PFET 414. If the data clocked into DFF 402 is a zero, node 420 is low and node 422 is high. In this case PFET 412 is in a conducting state and PFET 410 is in a non-conducting state. All current is shunted to ground and no current (except current due to leakage or subthreshold conduction pathways) reaches the output pad from this current source of the DAC. Conversely, if DATA is high at the clock, then node 420 goes high, node 422 goes low, PFET 412 is turned off, and PFET 410 conducts the current to OUT. As shown in FIG. 4, the switch control signal generator outputs are applied respectively to node 420 and node 422. Ideally, the current switch control signal generator output signals, as applied to nodes 420, 422, should cross at a voltage such that as one of the current switch transistors turns off, the other turns on at a complementary rate so that the total current through both transistors remains constant. In an ideal switch, the voltage on a node 416 between the current source and current switches would not change during switching. Node 416 is referred to herein as the TAIL node.
The size of the transistors used in the current source and switches is proportional to the current they must source and switch in order that the current density is substantially equal in all sources and switches. This causes the operating points of each current source to be substantially equal to that of all the others, and the operating points of the switches to be substantially equal, thereby providing close matching. All the switches and current sources in the linear section of the DAC are respectively equal in size and respectively twice the size of the largest value in the binary section.
The switching waveforms for the conventional switch control circuit of FIG. 4, are shown in FIG. 5. The waveforms in FIG. 5 illustrate some of the difficulties with conventional switch control circuits. The crossover voltage of nodes 420 and 422 are difficult to control using only inverters. When the switch points are not equally delayed from the clock, output glitches may form from hazards during multiple bits changing in different directions.
The difficulty of balancing delays is made worse by the different loads resulting from the different switch sizes. This requires the switch drivers to be tuned for each binary step and for the linear section to give uniform delay and crossover voltage for all variations in process, temperature and voltage; a very difficult task.
Also, as shown in FIG. 5, if the switch drivers cross at too high or too low a voltage, then the current in both switch transistors is not constant and excess charge is taken from the TAIL node or is allowed to build up on the TAIL node. This is seen as a non-constant value on the TAIL node. The extent to which this deficit or excess of charge is transferred to OUT also increases the glitch energy.
Conventional circuit configurations that are used to balance delays and cross-over voltage in an attempt to improve control of current switches have been dependent on inverter, pass gate or logic gate delays. These circuit configurations suffer from dependencies of manufacturing tolerances and operating conditions.
What is needed is a DAC that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions.
Briefly, a current mode DAC that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source.
In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included.
In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller to reduce timing differences between stages of the DAC.
Various other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.